1. Field of the Invention
The present invention relates in general to the field of electronic circuits. In one aspect, the present invention relates to a method and apparatus for biasing split power supply based circuits in response to power up conditions.
2. Description of the Related Art
In many integrated electronic circuits, multiple different voltage power supply levels are provided for different circuit portions, such as core logic, analog circuits and input output interfaces, and any other suitable circuits. With multi-voltage or “split-rail” circuits, each circuit portion may have different power levels, high drive voltage levels, and maximum allowable voltage levels, depending on the type of transistor technology and design used at each circuit portion. The use of different types of transistors and power supply levels can create design challenges since transistors can be damaged by excessive gate-source voltages (Vgs) that are created when power supply voltages are improperly supplied to the transistors. Accordingly, a reliability challenge for designing integrated circuits is to power up the split-rail circuit portions with a power-up circuit or sequence that keeps the gate-source voltage Vgs below a maximum allowable gate-source voltage Vgs-max.
Accordingly, a need exists for an improved power up circuit and methodology which addresses various problems in the art that have been discovered by the above-named inventor where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.